BibTeX record conf/cases/HameedBH13

download as .bib file

@inproceedings{DBLP:conf/cases/HameedBH13,
  author       = {Fazal Hameed and
                  Lars Bauer and
                  J{\"{o}}rg Henkel},
  title        = {Simultaneously optimizing {DRAM} cache hit latency and miss rate via
                  novel set mapping policies},
  booktitle    = {International Conference on Compilers, Architecture and Synthesis
                  for Embedded Systems, {CASES} 2013, Montreal, QC, Canada, September
                  29 - October 4, 2013},
  pages        = {11:1--11:10},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/CASES.2013.6662515},
  doi          = {10.1109/CASES.2013.6662515},
  timestamp    = {Mon, 05 Feb 2024 20:34:01 +0100},
  biburl       = {https://dblp.org/rec/conf/cases/HameedBH13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.