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BibTeX record conf/cases/HameedBH13
@inproceedings{DBLP:conf/cases/HameedBH13, author = {Fazal Hameed and Lars Bauer and J{\"{o}}rg Henkel}, title = {Simultaneously optimizing {DRAM} cache hit latency and miss rate via novel set mapping policies}, booktitle = {International Conference on Compilers, Architecture and Synthesis for Embedded Systems, {CASES} 2013, Montreal, QC, Canada, September 29 - October 4, 2013}, pages = {11:1--11:10}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/CASES.2013.6662515}, doi = {10.1109/CASES.2013.6662515}, timestamp = {Mon, 05 Feb 2024 20:34:01 +0100}, biburl = {https://dblp.org/rec/conf/cases/HameedBH13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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