Scott Little David Walter Nicholas Seegmiller Chris J. Myers Tomohiro Yoneda Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. 426-440 http://dx.doi.org/10.1007/978-3-540-30476-0_35 2004 conf/atva/2004 ATVA db/conf/atva/atva2004.html#LittleWSMY04