At-Speed Built-in Test for Logic Circuits with Multiple Clocks.

Kazumi Hatayama Michinobu Nakao Yasuo Sato At-Speed Built-in Test for Logic Circuits with Multiple Clocks. 292-297 2002 conf/ats/2002 Asian Test Symposium http://csdl.computer.org/comp/proceedings/ats/2002/1825/00/18250292abs.htm db/conf/ats/ats2002.html#HatayamaNS02