<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/async/ChelceaVG07" mdate="2007-05-02">
<author>Tiberiu Chelcea</author>
<author>Girish Venkataramani</author>
<author>Seth Copen Goldstein</author>
<title>Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis.</title>
<pages>117-128</pages>
<year>2007</year>
<crossref>conf/async/2007</crossref>
<booktitle>ASYNC</booktitle>
<ee>http://doi.ieeecomputersociety.org/10.1109/ASYNC.2007.10</ee>
<url>db/conf/async/async2007.html#ChelceaVG07</url>
</inproceedings>
</dblp>
