DBLP Record 'conf/async/ChelceaVG07'

BibTeX

@inproceedings{DBLP:conf/async/ChelceaVG07,
  author    = {Tiberiu Chelcea and
               Girish Venkataramani and
               Seth Copen Goldstein},
  title     = {Area Optimizations for Dual-Rail Circuits Using Relative-Timing
               Analysis},
  booktitle = {ASYNC},
  year      = {2007},
  pages     = {117-128},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2007.10},
  crossref  = {DBLP:conf/async/2007},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/async/2007,
  title     = {13th IEEE International Symposium on Asynchronous Circuits
               and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California,
               USA},
  booktitle = {ASYNC},
  publisher = {IEEE Computer Society},
  year      = {2007},
  isbn      = {978-0-7695-2771-0},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}