BibTeX record conf/async/BouzafourRG0S18

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@inproceedings{DBLP:conf/async/BouzafourRG0S18,
  author       = {Aymane Bouzafour and
                  Marc Renaudin and
                  Hubert Garavel and
                  Radu Mateescu and
                  Wendelin Serwe},
  title        = {Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous
                  Circuits},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {34--42},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00021},
  doi          = {10.1109/ASYNC.2018.00021},
  timestamp    = {Thu, 23 Mar 2023 23:58:24 +0100},
  biburl       = {https://dblp.org/rec/conf/async/BouzafourRG0S18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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