BibTeX record conf/asscc/ZhangCSTSHWWCHS19

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@inproceedings{DBLP:conf/asscc/ZhangCSTSHWWCHS19,
  author       = {Zhixiao Zhang and
                  Jia{-}Jing Chen and
                  Xin Si and
                  Yung{-}Ning Tu and
                  Jian{-}Wei Su and
                  Wei{-}Hsing Huang and
                  Jing{-}Hong Wang and
                  Wei{-}Chen Wei and
                  Yen{-}Cheng Chiu and
                  Je{-}Min Hong and
                  Shyh{-}Shyuan Sheu and
                  Sih{-}Han Li and
                  Ren{-}Shuo Liu and
                  Chih{-}Cheng Hsieh and
                  Kea{-}Tiong Tang and
                  Meng{-}Fan Chang},
  title        = {A 55nm 1-to-8 bit Configurable 6T {SRAM} based Computing-in-Memory
                  Unit-Macro for CNN-based {AI} Edge Processors},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
                  SAR, China, November 4-6, 2019},
  pages        = {217--218},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/A-SSCC47793.2019.9056933},
  doi          = {10.1109/A-SSCC47793.2019.9056933},
  timestamp    = {Sun, 19 Apr 2020 18:10:17 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/ZhangCSTSHWWCHS19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}