BibTeX record conf/asscc/MaSLR17

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@inproceedings{DBLP:conf/asscc/MaSLR17,
  author       = {Shunli Ma and
                  Jili Sheng and
                  Ning Li and
                  Junyan Ren},
  title        = {A 7GHz-bandwidth 31.5 GHz {FMCW-PLL} with novel twin-VCOs structure
                  in 65nm {CMOS}},
  booktitle    = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
                  Korea (South), November 6-8, 2017},
  pages        = {321--324},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ASSCC.2017.8240281},
  doi          = {10.1109/ASSCC.2017.8240281},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/asscc/MaSLR17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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