<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/aspdac/ZhangTCHC06" mdate="2007-06-04">
<author>Lizheng Zhang</author>
<author>Jeng-Liang Tsai</author>
<author>Weijen Chen</author>
<author>Yuhen Hu</author>
<author>Charlie Chung-Ping Chen</author>
<title>Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops.</title>
<pages>941-946</pages>
<year>2006</year>
<crossref>conf/aspdac/2006</crossref>
<booktitle>ASP-DAC</booktitle>
<ee>http://doi.acm.org/10.1145/1118299.1118511</ee>
<url>db/conf/aspdac/aspdac2006.html#ZhangTCHC06</url>
</inproceedings>
</dblp>
