An FPGA implementation of low-density parity-check code decoder with multi-rate capability.

Lei Yang Manyuan Shen Hui Liu C.-J. Richard Shi An FPGA implementation of low-density parity-check code decoder with multi-rate capability. 760-763 2005 conf/aspdac/2005 ASP-DAC http://doi.acm.org/10.1145/1120725.1121011 db/conf/aspdac/aspdac2005.html#YangSLS05