BibTeX record conf/aspdac/XuSZSL22

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@inproceedings{DBLP:conf/aspdac/XuSZSL22,
  author       = {Rui Xu and
                  Edwin Hsing{-}Mean Sha and
                  Qingfeng Zhuge and
                  Yuhong Song and
                  Jingzhi Lin},
  title        = {Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete
                  Memory Latency Hiding},
  booktitle    = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
                  2022, Taipei, Taiwan, January 17-20, 2022},
  pages        = {389--394},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ASP-DAC52403.2022.9712532},
  doi          = {10.1109/ASP-DAC52403.2022.9712532},
  timestamp    = {Fri, 15 Dec 2023 14:50:53 +0100},
  biburl       = {https://dblp.org/rec/conf/aspdac/XuSZSL22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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