Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs.

Tsung-Yi Wu Tzi-Wei Kao Shi-Yi Huang Tai-Lun Li How-Rern Lin Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. 444-449 2010 ASP-DAC http://dx.doi.org/10.1109/ASPDAC.2010.5419842 conf/aspdac/2010 db/conf/aspdac/aspdac2010.html#WuKHLL10