Low power clock buffer planning methodology in F-D placement for large scale circuit design.

Yanfeng Wang Qiang Zhou Yici Cai Jiang Hu Xianlong Hong Jinian Bian Low power clock buffer planning methodology in F-D placement for large scale circuit design. 370-375 2008 ASP-DAC http://dx.doi.org/10.1109/ASPDAC.2008.4483977 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#WangZCHHB08