DBLP Record 'conf/aspdac/WangZCHHB08'

BibTeX

@inproceedings{DBLP:conf/aspdac/WangZCHHB08,
  author    = {Yanfeng Wang and
               Qiang Zhou and
               Yici Cai and
               Jiang Hu and
               Xianlong Hong and
               Jinian Bian},
  title     = {Low power clock buffer planning methodology in F-D placement
               for large scale circuit design},
  booktitle = {ASP-DAC},
  year      = {2008},
  pages     = {370-375},
  ee        = {http://dx.doi.org/10.1109/ASPDAC.2008.4483977},
  crossref  = {DBLP:conf/aspdac/2008},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/aspdac/2008,
  title     = {Proceedings of the 13th Asia South Pacific Design Automation
               Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008},
  booktitle = {ASP-DAC},
  publisher = {IEEE},
  year      = {2008},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}