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BibTeX record conf/aspdac/WangTWOSL14
@inproceedings{DBLP:conf/aspdac/WangTWOSL14, author = {Jianxing Wang and Yenni Tim and Weng{-}Fai Wong and Zhong{-}Liang Ong and Zhenyu Sun and Hai Li}, title = {A coherent hybrid {SRAM} and {STT-RAM} {L1} cache architecture for shared memory multicores}, booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC} 2014, Singapore, January 20-23, 2014}, pages = {610--615}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ASPDAC.2014.6742958}, doi = {10.1109/ASPDAC.2014.6742958}, timestamp = {Mon, 26 Jun 2023 20:46:40 +0200}, biburl = {https://dblp.org/rec/conf/aspdac/WangTWOSL14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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