Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs.

Davide Pandini Primo Scandolara Carlo Guardiani Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs. 45-50 1998 ASP-DAC db/conf/aspdac/aspdac98.html#PandiniSG98