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@inproceedings{DBLP:conf/aspdac/PandiniSG98,
author = {Davide Pandini and
Primo Scandolara and
Carlo Guardiani},
title = {Reduced Order Macromodel of Coupled Interconnects for Timing
and Functional Verification of Sub Half-micron IC Designs},
booktitle = {ASP-DAC},
year = {1998},
pages = {45-50},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2002-01-03 by Michael Ley (ley@uni-trier.de)