<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/aspdac/LiuDHWHG08" mdate="2008-05-06">
<author>Jiayi Liu</author>
<author>Sheqin Dong</author>
<author>Xianlong Hong</author>
<author>Yibo Wang</author>
<author>Ou He</author>
<author>Satoshi Goto</author>
<title>Symmetry constraint based on mismatch analysis for analog layout in SOI technology.</title>
<pages>772-775</pages>
<year>2008</year>
<booktitle>ASP-DAC</booktitle>
<ee>http://dx.doi.org/10.1109/ASPDAC.2008.4484055</ee>
<crossref>conf/aspdac/2008</crossref>
<url>db/conf/aspdac/aspdac2008.html#LiuDHWHG08</url>
</inproceedings>
</dblp>
