Using GALS architecture to reduce the impact of long wire delay on FPGA performance.

Xin Jia Ranga Vemuri Using GALS architecture to reduce the impact of long wire delay on FPGA performance. 1260-1263 2005 conf/aspdac/2005 ASP-DAC http://doi.acm.org/10.1145/1120725.1121038 db/conf/aspdac/aspdac2005.html#JiaV05