High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.

Tetsuya Iizuka Makoto Ikeda Kunihiro Asada High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. 149-154 2004 conf/aspdac/2004 ASP-DAC http://doi.acm.org/10.1145/1015090.1015126 db/conf/aspdac/aspdac2004.html#IizukaIA04