BibTeX record conf/asicon/LongBLWL23

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@inproceedings{DBLP:conf/asicon/LongBLWL23,
  author       = {Honghong Long and
                  Yu Bai and
                  Yanze Li and
                  Jian Wang and
                  Jinmei Lai},
  title        = {Optimizing Wirelength And Delay of {FPGA} Tile through Floorplanning
                  Based on Simulated Annealing Algorithm},
  booktitle    = {15th {IEEE} International Conference on ASIC, {ASICON} 2023, Nanjing,
                  China, October 24-27, 2023},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.1109/ASICON58565.2023.10396538},
  doi          = {10.1109/ASICON58565.2023.10396538},
  timestamp    = {Fri, 16 Feb 2024 14:02:58 +0100},
  biburl       = {https://dblp.org/rec/conf/asicon/LongBLWL23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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