Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes.

Marcos B. S. Tavares Steffen Kunze Emil Matús Gerhard Fettweis Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. 215-220 2008 ASAP http://dx.doi.org/10.1109/ASAP.2008.4580181 conf/asap/2008 db/conf/asap/asap2008.html#TavaresKMF08