Reduced Latency IEEE Floating-Point Standard Adder Architectures.

Andrew Beaumont-Smith Neil Burgess S. Lefrere Cheng-Chew Lim Reduced Latency IEEE Floating-Point Standard Adder Architectures. 35- 1999 conf/arith/1999 IEEE Symposium on Computer Arithmetic http://csdl.computer.org/comp/proceedings/arith/1999/0116/00/01160035abs.htm db/conf/arith/arith1999.html#Beaumont-SmithBLL99