Maurice Keller Tim Kerins Francis M. Crowe William P. Marnane FPGA Implementation of a <i>GF</i>(2<sup><i>m</i></sup>) Tate Pairing Architecture. 358-369 2006 conf/arc/2006 ARC http://dx.doi.org/10.1007/11802839_44 db/conf/arc/arc2006.html#KellerKCM06