BibTeX record conf/apccas/RamV23

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@inproceedings{DBLP:conf/apccas/RamV23,
  author       = {Sadhu Sai Ram and
                  Kuruvilla Varghese},
  title        = {Efficient Hardware Design of Parameterized Posit Multiplier and Posit
                  Adder},
  booktitle    = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2023,
                  Hyderabad, India, November 19-22, 2023},
  pages        = {343--347},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.1109/APCCAS60141.2023.00083},
  doi          = {10.1109/APCCAS60141.2023.00083},
  timestamp    = {Fri, 10 May 2024 11:45:42 +0200},
  biburl       = {https://dblp.org/rec/conf/apccas/RamV23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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