BibTeX record conf/aicas/WangLHZCLKTT22

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@inproceedings{DBLP:conf/aicas/WangLHZCLKTT22,
  author       = {Xiaomeng Wang and
                  Xuejiao Liu and
                  Xianghong Hu and
                  Xiaopeng Zhong and
                  Xizi Chen and
                  Yu Liu and
                  Patrick Kong and
                  Fengshi Tian and
                  Chi{-}Ying Tsui},
  title        = {{TAC-RAM:} {A} 65nm 4Kb {SRAM} Computing-in-Memory Design with 57.55
                  {TOPS/W} supporting Multibit Matrix-Vector Multiplication for Binarized
                  Neural Network},
  booktitle    = {4th {IEEE} International Conference on Artificial Intelligence Circuits
                  and Systems, {AICAS} 2022, Incheon, Republic of Korea, June 13-15,
                  2022},
  pages        = {66--69},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/AICAS54282.2022.9869970},
  doi          = {10.1109/AICAS54282.2022.9869970},
  timestamp    = {Mon, 05 Feb 2024 20:34:20 +0100},
  biburl       = {https://dblp.org/rec/conf/aicas/WangLHZCLKTT22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}