BibTeX record conf/aicas/ChenWLDWY0GLZFY21

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@inproceedings{DBLP:conf/aicas/ChenWLDWY0GLZFY21,
  author       = {Wenxuan Chen and
                  Zheng Wang and
                  Ming Lei and
                  Bo Dong and
                  Zhuo Wang and
                  Yongkui Yang and
                  Chao Chen and
                  Weiyu Guo and
                  Chen Liang and
                  Qian Zhang and
                  Wenqi Fang and
                  Zhibin Yu},
  title        = {Improving system latency of {AI} accelerator with on-chip pipelined
                  activation preprocessing and multi-mode batch inference},
  booktitle    = {3rd {IEEE} International Conference on Artificial Intelligence Circuits
                  and Systems, {AICAS} 2021, Washington, DC, USA, June 6-9, 2021},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/AICAS51828.2021.9458529},
  doi          = {10.1109/AICAS51828.2021.9458529},
  timestamp    = {Wed, 08 Mar 2023 08:47:32 +0100},
  biburl       = {https://dblp.org/rec/conf/aicas/ChenWLDWY0GLZFY21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}