Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment.

Michael V. Goncharov Alexander B. Smirnov Nikolai Starodoubtsev Ilya V. Klotchkov Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment. 120- 1998 conf/acsd/1998 ACSD http://csdl.computer.org/comp/proceedings/csd/1998/8350/00/83500120abs.htm db/conf/acsd/acsd1998.html#GoncharovSSK98