Chris R. Jesshope Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. 80-88 2001 conf/aPcsac/2001 ACSAC http://doi.ieeecomputersociety.org/10.1109/ACAC.2001.903363 db/conf/aPcsac/aPcsac2001.html#Jesshope01