Jesshope01'

BibTeX

@inproceedings{DBLP:conf/aPcsac/Jesshope01,
  author    = {Chris R. Jesshope},
  title     = {Implementing an efficient vector instruction set in a chip
               multi-processor using micro-threaded pipelines},
  booktitle = {ACSAC},
  year      = {2001},
  pages     = {80-88},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/ACAC.2001.903363},
  crossref  = {DBLP:conf/aPcsac/2001},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/aPcsac/2001,
  title     = {6th Australasian Computer Systems Architecture Conference
               (ACSAC 2001), 29-30 January 2001, Gold Coast, Queensland,
               Australia},
  booktitle = {ACSAC},
  publisher = {IEEE Computer Society},
  year      = {2001},
  isbn      = {0-7695-0954-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}