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Geert Deconinck

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Murali Jayapala

> Home > Persons > Geert Deconinck

Publications

2006
[c56]
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  - conf/sips/AaJCCD06
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  - https://dblp.org/rec/conf/sips/AaJCCD06
Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck:
Instruction Transfer And Storage Exploration for Low Energy VLIWs. SiPS 2006: 292-297
2005
[j14]
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  - electronic edition @ iospress.com
  - no references & citations available
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  - journals/jec/AaJBDLCC05
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  - https://dblp.org/rec/journals/jec/AaJBDLCC05
Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor:
Instruction buffering exploration for low energy embedded processors. J. Embed. Comput. 1(3): 341-351 (2005)
[j13]
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  - journals/tc/JayapalaBACCD05
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  - https://dblp.org/rec/journals/tc/JayapalaBACCD05
Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck:
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. IEEE Trans. Computers 54(6): 672-683 (2005)
[c54]
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  dblp key:
  - conf/asap/LambrechtsRLTAJCVDCRC05
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  - https://dblp.org/rec/conf/asap/LambrechtsRLTAJCVDCRC05
Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina:
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. ASAP 2005: 179-184
2004
[c51]
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  - conf/aspdac/AaJBDLCC04
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  - https://dblp.org/rec/conf/aspdac/AaJBDLCC04
Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal:
Instruction buffering exploration for low energy VLIWs with instruction clusters. ASP-DAC 2004: 824-829
[c47]
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  - conf/patmos/JayapalaABCCD04
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Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck:
L0 Cluster Synthesis and Operation Shuffling. PATMOS 2004: 311-321
[c46]
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  dblp key:
  - conf/rtss/LambrechtsAJTLSBMCVDCRB04
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  - https://dblp.org/rec/conf/rtss/LambrechtsAJTLSBMCVDCRB04
Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll:
Design Style Case Study for Embedded Multi Media Compute Nodes. RTSS 2004: 104-113
[c45]
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  - conf/sac/JayapalaABDCC04
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Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal:
L0 buffer energy optimization through scheduling and exploration. SAC 2004: 905-906
2003
[c42]
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  dblp key:
  - conf/fpl/BaratJALDC03
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  - https://dblp.org/rec/conf/fpl/BaratJALDC03
Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, Henk Corporaal:
Low Power Coarse-Grained Reconfigurable Instruction Set Processor. FPL 2003: 230-239
[c37]
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  - conf/patmos/AaJBDLCC03
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Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor:
Instruction Buffering Exploration for Low Energy Embedded Processors. PATMOS 2003: 409-419
2002
[j8]
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  - journals/jcsc/MarchalJSYCD02
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Paul Marchal, Murali Jayapala, Samuel Xavier de Souza, Peng Yang, Francky Catthoor, Geert Deconinck:
Matador: An Exploration Environment for System-Design. J. Circuits Syst. Comput. 11(5): 503-536 (2002)
[c29]
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  - conf/patmos/JayapalaBBCDC02
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Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal:
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. PATMOS 2002: 258-267
[c27]
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  - conf/vlsid/BaratJBD02
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Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck:
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. ASP-DAC/VLSI Design 2002: 338-344

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