Yuen H. Chan

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Pradip Patel

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Publications

2013
[c14]
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John Davis, Paul Bunce, Diana M. Henderson, Yuen H. Chan, Uma Srinivasan, Daniel Rodko, Pradip Patel, Thomas J. Knips, Tobias Werner:
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor. ISSCC 2013: 324-325
2012
[j8]
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James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott:
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. IEEE J. Solid State Circuits 47(1): 151-163 (2012)
2011
[c12]
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  - conf/isscc/PelellaCBPRS11
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Antonio Pelella, Yuen H. Chan, Bargav Balakrishnan, Pradip Patel, Daniel Rodko, Richard E. Serton:
Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor. ISSCC 2011: 72-73
2006
[c9]
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John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC 2006: 2564-2571

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