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Paul E. Hasler
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Publications
- 2006
- [j12]Abhishek Bandyopadhyay, Jungwon Lee, Ryan W. Robucci, Paul E. Hasler:
MATIA: a programmable 80 WμW/frame CMOS block matrix transform imager architecture. IEEE J. Solid State Circuits 41(3): 663-672 (2006) - [j11]Abhishek Bandyopadhyay, Guillermo J. Serrano, Paul E. Hasler:
Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades. IEEE J. Solid State Circuits 41(9): 2107-2114 (2006) - 2005
- [c72]Jungwon Lee, Abhishek Bandyopadhyay, I. Faik Baskaya, Ryan W. Robucci, Paul E. Hasler:
Image processing system using a programmable transform imager. ICASSP (5) 2005: 101-104 - [c67]Abhishek Bandyopadhyay, Guillermo J. Serrano, Paul E. Hasler:
Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method. ISCAS (3) 2005: 2148-2151 - [c60]Abhishek Bandyopadhyay, Jungwon Lee, Ryan W. Robucci, Paul E. Hasler:
A 80µW/frame 104×128 CMOS imager front end for JPEG compression. ISCAS (5) 2005: 5318-5321 - 2004
- [c52]Ravi Chawla, Abhishek Bandyopadhyay, Venkatesh Srinivasan, Paul E. Hasler:
A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity. CICC 2004: 651-654 - 2003
- [j4]Paul E. Hasler, Abhishek Bandyopadhyay, David V. Anderson:
High Fill-Factor Imagers for Neuromorphic Processing Enabled by Floating-Gate Circuits. EURASIP J. Adv. Signal Process. 2003(7): 676-689 (2003) - [c31]Abhishek Bandyopadhyay, Paul E. Hasler:
A fully programmable CMOS block matrix transform imager architecture. CICC 2003: 189-192 - 2002
- [c22]Paul E. Hasler, Abhishek Bandyopadhyay, Paul D. Smith:
A matrix transform imager allowing high-fill factor. ISCAS (3) 2002: 337-340
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