Yi-Hau Chen

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shao-Yi Chien

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Publications

2010
[j6]
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Tzu-Der Chuang, Yu-Jen Chen, Yi-Hau Chen, Shao-Yi Chien, Liang-Gee Chen:
Architecture Design of Fine Grain Quality Scalable Encoder with CABAC for H.264/AVC Scalable Extension. J. Signal Process. Syst. 60(3): 363-375 (2010)
2008
[j5]
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  - journals/tcsv/ChenCCCCC08
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Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching-Yeh Chen, Shao-Yi Chien, Liang-Gee Chen:
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine. IEEE Trans. Circuits Syst. Video Technol. 18(1): 98-109 (2008)
[j4]
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Yi-Hau Chen, Shao-Yi Chien, Ching-Yeh Chen, Yu-Wen Huang, Liang-Gee Chen:
Analysis and Hardware Architecture Design of Global Motion Estimation. J. Signal Process. Syst. 53(3): 285-300 (2008)
[j3]
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  - journals/vlsisp/ChenCCHC08a
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Yi-Hau Chen, Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen:
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC. J. Signal Process. Syst. 53(3): 335-347 (2008)
2007
[c9]
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  - conf/sips/ChenCCLCC07
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Yu-Jen Chen, Yi-Hau Chen, Tzu-Der Chuang, Chung-Te Li, Shao-Yi Chien, Liang-Gee Chen:
Architecture Design of Fine Grain SNR Scalable Encoder with CABAC for H.264/AVC Scalable Extension. SiPS 2007: 515-520
2006
[j1]
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  - journals/tsp/ChenHCCC06
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Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Shao-Yi Chien, Liang-Gee Chen:
System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering. IEEE Trans. Signal Process. 54(10): 4004-4014 (2006)
2003
[c1]
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  - conf/icmcs/ChenCCHC03
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Ching-Yeh Chen, Shao-Yi Chien, Yi-Hau Chen, Yu-Wen Huang, Liang-Gee Chen:
Unsupervised object-based sprite coding system for tennis sport. ICME 2003: 337-340

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