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ORCIDJosé Nelson Amaral
- > Home > Persons > José Nelson Amaral
Publications
- 2023
[j39]Braedy Kuzma, Ivan Korostelev, João P. L. de Carvalho
, José E. Moreira, Christopher Barton, Guido Araujo, José Nelson Amaral:
Fast matrix multiplication via compiler-only layered data reorganization and intrinsic lowering. Softw. Pract. Exp. 53(9): 1793-1814 (2023)- [j37]Victor Ferrari, Rafael Cardoso Fernandes Sousa, Márcio Machado Pereira, Joao P. L. de Carvalho, José Nelson Amaral, José E. Moreira, Guido Araujo:
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions. ACM Trans. Archit. Code Optim. 20(4): 54:1-54:26 (2023) - [i5]Victor Ferrari, Rafael C. F. Sousa, Márcio Machado Pereira, João P. L. de Carvalho, José Nelson Amaral, José E. Moreira, Guido Araujo:
Advancing Direct Convolution using Convolution Slicing Optimization and ISA Extensions. CoRR abs/2303.04739 (2023) - [i4]Braedy Kuzma, Ivan Korostelev, João P. L. de Carvalho, José E. Moreira, Christopher Barton, Guido Araujo, José Nelson Amaral:
Fast Matrix Multiplication via Compiler-only Layered Data Reorganization and Intrinsic Lowering. CoRR abs/2305.18236 (2023) - 2022
- [c84]Victor Ferrari, Rafael C. F. Sousa, Márcio Machado Pereira, João P. L. de Carvalho, José Nelson Amaral, Guido Araujo:
Improving Convolution via Cache Hierarchy Tiling and Reduced Packing. PACT 2022: 538-539 - 2021
- [j33]João P. L. de Carvalho, Braedy Kuzma, Ivan Korostelev, José Nelson Amaral, Christopher Barton, José E. Moreira, Guido Araujo:
KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls. ACM Trans. Archit. Code Optim. 18(3): 38:1-38:22 (2021) - [c80]Caio S. Rohwedder, João P. L. de Carvalho, José Nelson Amaral, Guido Araújo, Giancarlo Colmenares, Kai-Ting Amy Wang:
Pooling Acceleration in the DaVinci Architecture Using Im2col and Col2im Instructions. IPDPS Workshops 2021: 46-55 - 2018
- [j29]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation. IEEE Trans. Parallel Distributed Syst. 29(2): 466-480 (2018) - 2017
- [c69]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories. Euro-Par 2017: 607-621 - 2016
- [j27]Márcio Machado Pereira, Matthew Gaudet, José Nelson Amaral, Guido Araujo:
Study of hardware transactional memory characteristics and serialization policies on Haswell. Parallel Comput. 54: 46-58 (2016) - [c68]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories. IPDPS 2016: 586-595 - 2015
- [j22]Guido Araujo, Jean-Luc Gaudiot, Manish Parashar, Derek Chiou, José Nelson Amaral, Chita R. Das:
Guest Editorial: SBAC-PAD 2013. Int. J. Parallel Program. 43(6): 961-964 (2015) - [c64]Juan Salamanca, José Nelson Amaral, Guido Araujo:
Using Hardware Transactional Memory to Enable Speculative Trace Optimization. SBAC-PAD (Workshops) 2015: 1-6 - [c63]Matthew Gaudet, Guido Araujo, José Nelson Amaral:
Serialization Management for Best-Effort Hardware Transactional Memory. SBAC-PAD 2015: 138-145 - 2014
- [c59]Márcio Machado Pereira, José Nelson Amaral, Guido Araujo:
Measuring Effective Work to Reward Success in Dynamic Transaction Scheduling. ICPP 2014: 141-150 - [c57]Márcio Machado Pereira, Matthew Gaudet, José Nelson Amaral, Guido Araujo:
Multi-dimensional Evaluation of Haswell's Transactional Memory Performance. SBAC-PAD 2014: 144-151
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