Jia-Ching Wang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Tai-Haur Kuo

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Publications

2023
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Jia-Ching Wang, Tai-Haur Kuo:
A 3mW 2.7GS/s 8b Subranging ADC with Multiple-Reference-Reference-Embedded Comparators. ISSCC 2023: 276-277
2022
[j58]
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Jia-Ching Wang, Tai-Haur Kuo:
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier. IEEE J. Solid State Circuits 57(12): 3794-3803 (2022)
[c116]
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Jia-Ching Wang, Tai-Haur Kuo:
A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend. ISSCC 2022: 162-164
[c111]
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Jia-Ching Wang, Bing-Yang Li, Tai-Haur Kuo:
A 9.8-fJ/conv.-step FoMW 8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators. VLSI Technology and Circuits 2022: 92-93
2020
[j51]
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Jia-Ching Wang, Tsung-Chih Hung, Tai-Haur Kuo:
A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique. IEEE J. Solid State Circuits 55(12): 3271-3280 (2020)
[c95]
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Tsung-Chih Hung, Jia-Ching Wang, Tai-Haur Kuo:
16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme. ISSCC 2020: 256-258
2019
[c81]
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Jia-Ching Wang, Tsung-Chih Hung, Tai-Haur Kuo:
A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique. VLSI-DAT 2019: 1-3

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