Ru Huang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jihang Gao

> Home > Persons > Ru Huang

Publications

2024
[c120]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/XuYLGLCZHSY24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/XuYLGLCZHSY24
Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Hao Zhang, Ru Huang, Linxiao Shen, Le Ye:
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. ISSCC 2024: 72-74
[c119]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/YeSGLCXCZZYH24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/YeSGLCXCZZYH24
Siyuan Ye, Linxiao Shen, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Hao Zhang, Xing Zhang, Le Ye, Ru Huang:
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. ISSCC 2024: 168-170
[c118]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/ChenSYGLCXLZYH24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/ChenSYGLCXLZYH24
Zhuoyi Chen, Linxiao Shen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Hao Zhang, Le Ye, Ru Huang:
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. ISSCC 2024: 174-176
2023
[c101]
- view
  authority control:
- export record
  dblp key:
  - conf/esscirc/XuSYWCGCZHY23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/XuSYWCGCZHY23
Xinhang Xu, Linxiao Shen, Siyuan Ye, Jiayi Wu, Zhuoyi Chen, Jihang Gao, Jiajia Cui, Yihan Zhang, Ru Huang, Le Ye:
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. ESSCIRC 2023: 121-124
[c87]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/GaoSLYLXCGHY23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/GaoSLYLXCGHY23
Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye:
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. ISSCC 2023: 346-347
2022
[c70]
- view
  authority control:
- export record
  dblp key:
  - conf/isscc/ZhangXWLGCLSSRY22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/ZhangXWLGCLSSRY22
Yihan Zhang, Chang Xue, Xiao Wang, Tianyi Liu, Jihang Gao, Peiyu Chen, Jinguang Liu, Linan Sun, Linxiao Shen, Jiayoon Ru, Le Ye, Ru Huang:
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. ISSCC 2022: 184-186

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.