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ORCIDJulian Viejo
- > Home > Persons > Julian Viejo
Publications
- 2020
[j10]David Guerrero Martos
, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa:
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020(1): 1-21 (2020)- [j9]David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa:
Address-encoded byte order. Microprocess. Microsystems 78: 103268 (2020) - 2017
- [j8]Paulino Ruiz-de-Clavijo, Enrique Ostúa, Manuel Jesús Bellido Díaz, Jorge Juan, Julian Viejo, David Guerrero Martos:
Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. 67: 32-37 (2017) - 2012
- [j6]Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Enrique Ostúa, Juan Quiros:
Long-term on-chip verification of systems with logical events scattered in time. Microprocess. Microsystems 36(5): 402-408 (2012) - 2011
- [j5]David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7(3): 444-452 (2011) - 2010
- [c7]Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Manuel Jesús Bellido Díaz, Enrique Ostúa:
Design and implementation of a suitable core for on-chip long-term verification. SIES 2010: 234-237 - 2007
- [j2]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3(1): 70-77 (2007) - [c5]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo:
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412 - [c4]Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz:
Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340 - 2006
- [j1]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa, Julian Viejo:
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2(1): 87-94 (2006) - [c3]Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos:
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES 2006: 1-7 - 2005
- [c2]Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo:
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347 - [c1]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo:
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435
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