Hyun-Woo Lee

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Kwang Hyun Kim

> Home > Persons > Hyun-Woo Lee

Publications

2012
[j8]
- view
  authority control:
- export record
  dblp key:
  - journals/jssc/LeeCSKKKKJKPKKCRCKKCC12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/LeeCSKKKKJKPKKCRCKKCC12
Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits 47(6): 1436-1447 (2012)
2010
[c14]
- view
  authority control:
- export record
  dblp key:
  - conf/iscas/LeeKYPLKKJKRKCKCCK10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/LeeKYPLKKJKRKCKCCK10
Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih:
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. ISCAS 2010: 3861-3864

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.