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Sang Lyul Min
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Publications
- 2011
- [j33]Seungkyun Kim, Kiwon Kwon, Chihun Kim, Choonki Jang, Jaejin Lee, Sang Lyul Min:
Demand Paging Techniques for Flash Memory Using Compiler Post-Pass Optimizations. ACM Trans. Embed. Comput. Syst. 10(4): 40:1-40:29 (2011) - 2010
- [j32]Yoon Jae Seong, Eyee Hyun Nam, Jinhyuk Yoon, Hongseok Kim, Jin-Yong Choi, Sookwan Lee, Young Hyun Bae, Jaejin Lee, Yookun Cho, Sang Lyul Min:
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture. IEEE Trans. Computers 59(7): 905-921 (2010) - [j31]Bernhard Egger, Seungkyun Kim, Choonki Jang, Jaejin Lee, Sang Lyul Min, Heonshik Shin:
Scratchpad Memory Management Techniques for Code in Embedded Systems without an MMU. IEEE Trans. Computers 59(8): 1047-1062 (2010) - 2007
- [j24]Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min:
Selective code transformation for dual instruction set processors. ACM Trans. Embed. Comput. Syst. 6(2): 10 (2007) - 2006
- [c43]Bernhard Egger, Chihun Kim, Choonki Jang, Yoonsung Nam, Jaejin Lee, Sang Lyul Min:
A dynamic code placement technique for scratchpad memory using postpass optimization. CASES 2006: 223-233 - 2004
- [c42]Chanik Park, Junghee Lim, Kiwon Kwon, Jaejin Lee, Sang Lyul Min:
Compiler-assisted demand paging for embedded systems with flash memory. EMSOFT 2004: 114-124 - [c40]Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min:
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. SCOPES 2004: 244-258 - 2003
- [c38]Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson:
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. SCOPES 2003: 33-48 - [c37]Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min:
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. WCET 2003: 91-94
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