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Miguel Corbalan
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Publications
- 2005
- [j5]Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man:
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications. IEEE Trans. Computers 54(1): 76-81 (2005) - 2003
- [c18]Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex:
Global interconnect trade-off for technology over memory modules to application level: case study. SLIP 2003: 125-132 - 2002
- [c14]Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex:
Interconnect exploration for future wire dominated technologies. SLIP 2002: 105-106 - 2001
- [c12]Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man:
Cache conscious data layout organization for embedded multimedia applications. DATE 2001: 686-693 - 1999
- [j2]Diederik Verkest, Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Kris Croes, Miguel Miranda, Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Hugo De Man:
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management. J. VLSI Signal Process. 21(3): 185-194 (1999) - 1998
- [j1]Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man:
High-level address optimization and synthesis techniques for data-transfer-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 677-686 (1998) - [c6]Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man:
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. DAC 1998: 76-81 - 1997
- [c5]Miguel Miranda, M. Kaspar, Francky Catthoor, Hugo De Man:
Architectural exploration and optimization for counter based hardware address generation. ED&TC 1997: 293-298 - 1996
- [c4]Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man:
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures. ISSS 1996: 20-25
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