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ORCIDPhilip H. W. Leong
- > Home > Persons > Philip H. W. Leong
Publications
- 2020
[j44]Nicholas J. Fraser, Philip H. W. Leong
:
Kernel Normalised Least Mean Squares with Delayed Model Adaptation. ACM Trans. Reconfigurable Technol. Syst. 13(2): 7:1-7:30 (2020)- 2018
- [c122]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC 2018: 29-42 - [c121]Julian Faraone, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong:
SYQ: Learning Symmetric Quantization for Efficient Deep Neural Networks. CVPR 2018: 4300-4309 - [c117]Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland:
Customizing Low-Precision Deep Neural Networks for FPGAs. FPL 2018: 97-100 - [i6]Julian Faraone, Nicholas J. Fraser, Michaela Blott, Philip Heng Wai Leong:
SYQ: Learning Symmetric Quantization For Efficient Deep Neural Networks. CoRR abs/1807.00301 (2018) - [i5]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR abs/1807.10577 (2018) - 2017
- [j30]Nicholas J. Fraser, JunKyu Lee, Duncan J. M. Moss, Julian Faraone, Stephen Tridgell, Craig T. Jin, Philip Heng Wai Leong:
FPGA Implementations of Kernel Normalised Least Mean Squares Processors. ACM Trans. Reconfigurable Technol. Syst. 10(4): 26:1-26:20 (2017) - [c111]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. FPGA 2017: 65-74 - [c109]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
Scaling Binarized Neural Networks on Reconfigurable Logic. PARMA-DITAM@HiPEAC 2017: 25-30 - [c106]Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong:
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. ICONIP (2) 2017: 393-404 - [i4]Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
Scaling Binarized Neural Networks on Reconfigurable Logic. CoRR abs/1701.03400 (2017) - [i3]Julian Faraone, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong:
Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks. CoRR abs/1709.06262 (2017) - 2016
- [j27]Yeyong Pang, Shaojun Wang, Yu Peng, Xiyuan Peng, Nicholas J. Fraser, Philip Heng Wai Leong:
A Microcoded Kernel Recursive Least Squares Processor Using FPGA Technology. ACM Trans. Reconfigurable Technol. Syst. 10(1): 5:1-5:22 (2016) - [i2]Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. CoRR abs/1612.07119 (2016) - 2015
- [c98]Nicholas J. Fraser, Duncan J. M. Moss, JunKyu Lee, Stephen Tridgell, Craig T. Jin, Philip Heng Wai Leong:
A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation. FPL 2015: 1-6 - [c95]Stephen Tridgell, Duncan J. M. Moss, Nicholas J. Fraser, Philip Heng Wai Leong:
Braiding: A scheme for resolving hazards in kernel adaptive filters. FPT 2015: 136-143 - [c93]Nicholas J. Fraser, Duncan J. M. Moss, Nicolas Epain, Philip Heng Wai Leong:
Distributed kernel learning using Kernel Recursive Least Squares. ICASSP 2015: 5500-5504 - 2014
- [c88]Duncan J. M. Moss, Zhe Zhang, Nicholas J. Fraser, Philip Heng Wai Leong:
An FPGA-based spectral anomaly detection system. FPT 2014: 175-182 - 2013
- [c83]Yeyong Pang, Shaojun Wang, Yu Peng, Nicholas J. Fraser, Philip Heng Wai Leong:
A low latency kernel recursive least squares processor using FPGA technology. FPT 2013: 144-151
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