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Murad Qasaimeh

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Phillip H. Jones

> Home > Persons > Murad Qasaimeh

Publications

2021
[j3]
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  - journals/jsa/QasaimehDKBLHVZ21
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  - https://dblp.org/rec/journals/jsa/QasaimehDKBLHVZ21
Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones:
Benchmarking vision kernels and neural network inference accelerators on embedded platforms. J. Syst. Archit. 113: 101896 (2021)
[c9]
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  - conf/asap/QasaimehZJ21
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Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers. ASAP 2021: 250-257
2019
[c8]
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  - conf/fccm/QasaimehZJDLV19
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Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers:
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms. FCCM 2019: 336
[c7]
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  - conf/icess/QasaimehDLVZJ19
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Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones:
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. ICESS 2019: 1-8
[i2]
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  dblp key:
  - journals/corr/abs-1906-11879
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Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones:
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels. CoRR abs/1906.11879 (2019)
2018
[c6]
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  - conf/fpl/QasaimehZJ18
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Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors. FPL 2018: 351-354
2017
[c3]
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  - conf/ipps/QasaimehZJ17
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Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones:
A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization. IPDPS Workshops 2017: 106-114

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