Arun K. Somani

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Naga Durga Prasad Avirneni

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Publications

2016
[j77]
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Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani:
Managing contamination delay to improve Timing Speculation architectures. PeerJ Comput. Sci. 2: e79 (2016)
[j75]
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Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani:
Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors. IEEE Trans. Computers 65(3): 979-991 (2016)
[i2]
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Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani:
Managing contamination delay to improve Timing Speculation architectures. PeerJ Prepr. 4: e1412 (2016)
2015
[i1]
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  - journals/peerjpre/AvirneniRS15
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Naga Durga Prasad Avirneni, Prem Ramesh, Arun K. Somani:
Managing contamination delay to improve Timing Speculation architectures. PeerJ Prepr. 3: e1412 (2015)
2014
[j73]
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  - journals/tc/AvirneniS14
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Naga Durga Prasad Avirneni, Arun K. Somani:
Countering Power Analysis Attacks UsingReliable and Aggressive Designs. IEEE Trans. Computers 63(6): 1408-1420 (2014)
2012
[j68]
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  - journals/tc/AvirneniS12
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Naga Durga Prasad Avirneni, Arun K. Somani:
Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs. IEEE Trans. Computers 61(4): 488-501 (2012)
2009
[c123]
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  - conf/dsn/AvirneniSS09
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Naga Durga Prasad Avirneni, Viswanathan Subramanian, Arun K. Somani:
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems. DSN 2009: 185-194
2007
[c110]
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  - conf/dsn/SubramanianBAS07
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Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani:
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning. DSN 2007: 196-205

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