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Antonio Pullini
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Publications
- 2022
- [j15]Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. IEEE J. Solid State Circuits 57(1): 127-139 (2022) - 2021
- [c33]Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. ISSCC 2021: 60-62 - [i5]Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini:
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. CoRR abs/2110.09101 (2021) - 2019
- [j13]Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini:
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing. IEEE J. Solid State Circuits 54(7): 1970-1981 (2019) - 2018
- [j11]Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini:
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs 65-II(8): 1094-1098 (2018) - [c31]Eric Flamand, Davide Rossi, Francesco Conti, Igor Loi, Antonio Pullini, Florent Rotenberg, Luca Benini:
GAP-8: A RISC-V SoC for AI at the Edge of the IoT. ASAP 2018: 1-4 - [c30]Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini:
Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing. ESSCIRC 2018: 274-277 - 2017
- [j10]Davide Rossi, Igor Loi, Antonio Pullini, Thomas Christoph Müller, Andreas Burg, Francesco Conti, Luca Benini, Philippe Flatresse:
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. IEEE Des. Test 34(6): 46-53 (2017) - [j9]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini:
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j8]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2481-2494 (2017) - [j7]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2700-2713 (2017) - 2016
- [j6]Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini:
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision. J. Signal Process. Syst. 84(3): 339-354 (2016) - [c24]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini:
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c23]Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini:
A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. ISCAS 2016: 2910 - [i2]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR abs/1608.08376 (2016) - [i1]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR abs/1612.05974 (2016) - 2015
- [c21]Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini:
PULP: A parallel ultra low power platform for next generation IoT applications. Hot Chips Symposium 2015: 1-39 - 2014
- [c15]Francesco Conti, Davide Rossi, Antonio Pullini, Igor Loi, Luca Benini:
Energy-efficient vision on the PULP platform for ultra-low power parallel computing. SiPS 2014: 274-279 - 2011
- [j4]Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011) - 2010
- [c13]Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini:
3D NoCs - Unifying inter & intra chip communication. ISCAS 2010: 3337-3340
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