Остановите войну!
for scientists:
default search action
Jing-Yang Jou
- > Home > Persons > Jing-Yang Jou
Publications
- 2023
- [c82]Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang:
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. VLSI-SoC 2023: 1-6 - 2016
- [c76]Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou:
Chain-based pin count minimization for general-purpose digital microfluidic biochips. ASP-DAC 2016: 599-604 - 2014
- [j41]Bu-Ching Lin, Juinn-Dar Huang, Jing-Yang Jou:
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(4): 931-939 (2014) - [j40]Bu-Ching Lin, Ming-En Shih, Juinn-Dar Huang, Jing-Yang Jou:
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. J. Inf. Sci. Eng. 30(4): 991-1014 (2014) - 2012
- [j36]Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou:
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 559-566 (2012) - 2011
- [c68]Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC 2011: 497-502 - 2010
- [j35]Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou:
FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010) - [c64]Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou:
Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC 2010: 188-192 - 2009
- [j32]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 723-727 (2009) - 2008
- [j31]Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou:
Verification of Pin-Accurate Port Connections. IEEE Des. Test Comput. 25(5): 478-486 (2008) - 2007
- [c61]Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou:
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC 2007: 165-170 - 2006
- [c60]Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453 - [c59]Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou:
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC 2006: 600-605 - 2005
- [c55]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. HLDVT 2005: 87-93 - 2004
- [c43]Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang:
Verification on Port Connections. ITC 2004: 830-836 - 2001
- [j14]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 251-260 (2001) - 2000
- [j10]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 392-400 (2000) - 1998
- [j6]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang:
On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 634-642 (1998) - [c18]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717 - 1997
- [c16]Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei:
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC 1997: 259-264 - 1996
- [c11]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17 - 1995
- [c8]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from , , and to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 01:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint