Stephen Dean Brown

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Deshanand P. Singh

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Publications

2007
[j11]
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Deshanand P. Singh, Stephen Dean Brown:
An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integr. 40(2): 167-173 (2007)
[j10]
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  - journals/tcad/LingSB07
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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1196-1210 (2007)
[j9]
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  - journals/tvlsi/ManohararajahCSB07
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Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 895-903 (2007)
[c37]
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  - conf/vlsi/LingSB07
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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for structured ASICs using the transportation problem. VLSI-SoC 2007: 172-177
2006
[c33]
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  - conf/iccad/ChiuSMB06
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Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142
[c32]
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  - conf/slip/ManohararajahCSB06
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Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8
2005
[c31]
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  - conf/cicc/SinghMB05
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Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Two-stage physical synthesis for FPGAs. CICC 2005: 171-178
[c30]
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  - conf/dac/LingSB05
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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA technology mapping: a study of optimality. DAC 2005: 427-432
[c29]
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Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Incremental retiming for FPGA physical synthesis. DAC 2005: 433-438
[c28]
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  - conf/fpl/LingSB05
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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL 2005: 19-24
[c27]
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  - conf/fpl/ManohararajahSB05
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Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown:
Post-Placement BDD-Based Decomposition for FPGAs. FPL 2005: 31-38
[c25]
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  - conf/sat/LingSB05
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Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT 2005: 444-450
2004
[c24]
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  - conf/fpt/MalhotraBSB04
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Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown:
The Quartus University Interface Program: enabling advanced FPGA research. FPT 2004: 225-230
2003
[c20]
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  - conf/vlsi/SinghBB03
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Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown:
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI 2003: 28-33
[c19]
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Deshanand P. Singh, Stephen Dean Brown:
An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI 2003: 41-50
2002
[c17]
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  - conf/fpga/SinghB02
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Deshanand P. Singh, Stephen Dean Brown:
Integrated retiming and placement for field programmable gate arrays. FPGA 2002: 67-76
[c16]
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  - conf/fpga/SinghB02a
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Deshanand P. Singh, Stephen Dean Brown:
Constrained clock shifting for field programmable gate arrays. FPGA 2002: 121-126
[c13]
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  - conf/iccad/SinghB02
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Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for layout driven optimizations on FPGAs. ICCAD 2002: 752-759
2001
[c12]
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  - conf/fpga/SinghB01
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Deshanand P. Singh, Stephen Dean Brown:
The case for registered routing switches in field programmable gate arrays. FPGA 2001: 161-169

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