Stephen A. Szygenda

◀ ▶ joint publications with Edward W. Thompson

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Publications

1976
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Stephen A. Szygenda, Edward W. Thompson:
Modeling and Digital Simulation for Design Verification and Diagnosis. IEEE Trans. Computers 25(12): 1242-1253 (1976)
1975
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Stephen A. Szygenda, Edward W. Thompson:
Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer 8(3): 24-36 (1975)
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Edward W. Thompson, Stephen A. Szygenda:
Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer 8(3): 38-49 (1975)
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Edward W. Thompson, Stephen A. Szygenda:
Three levels of accuracy for the simulation of different fault types in digital systems. DAC 1975: 105-113
1974
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Edward W. Thompson, Stephen A. Szygenda, N. Billawala, R. Pierce:
Timing analysis for digital fault simulation using assignable delays. DAC 1974: 266-272
1972
[c5]
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Stephen A. Szygenda, Edward W. Thompson:
Fault insertion techniques and models for digital logic simulation. AFIPS Fall Joint Computing Conference (2) 1972: 875-884
1970
[c1]
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Stephen A. Szygenda, David M. Rouse, Edward W. Thompson:
A model and implementation of a universal time delay simulator for large digital nets. AFIPS Spring Joint Computing Conference 1970: 207-216

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