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Philippe Hoogvorst
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Publications
- 2016
- [c21]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache:
Improving the Big Mac Attack on Elliptic Curve Cryptography. The New Codebreakers 2016: 374-386 - 2015
- [i5]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache:
Improving the Big Mac Attack on Elliptic Curve Cryptography. IACR Cryptol. ePrint Arch. 2015: 819 (2015) - 2013
- [j6]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache:
A synthesis of side-channel attacks on elliptic curve cryptography in smart-cards. J. Cryptogr. Eng. 3(4): 241-265 (2013) - [c20]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache:
Dynamic countermeasure against the Zero Power Analysis. ISSPIT 2013: 140-147 - [i4]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache:
Dynamic Countermeasure Against the Zero Power Analysis. IACR Cryptol. ePrint Arch. 2013: 764 (2013) - 2012
- [c19]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache:
Low-Cost Countermeasure against RPA. CARDIS 2012: 106-122 - [c18]Cédric Murdica, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst, David Naccache:
Same Values Power Analysis Using Special Points on Elliptic Curves. COSADE 2012: 183-198 - 2011
- [i3]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback. CoRR abs/1103.1360 (2011) - 2009
- [j4]Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst:
High speed true random number generator based on open loop structures in FPGAs. Microelectron. J. 40(11): 1650-1656 (2009) - 2008
- [c14]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 - [c13]Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger:
An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC 2008: 120-125 - [c12]Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley:
Efficient tiling patterns for reconfigurable gate arrays. FPGA 2008: 257 - [c11]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst:
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL 2008: 161-166 - [c10]Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong:
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32 - [c9]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger:
Efficient tiling patterns for reconfigurable gate arrays. SLIP 2008: 11-18 - [i2]Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet:
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks. CoRR abs/0809.3942 (2008) - 2007
- [c8]Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst:
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT 2007: 369-372 - 2006
- [c6]Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst:
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. ReConFig 2006: 47-55
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