Ryuichi Fujimoto

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Mizuki Motoyoshi

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Publications

2013
[j20]
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Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Minoru Fujishima:
A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 486-493 (2013)
[j17]
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Minoru Fujishima, Mizuki Motoyoshi, Kosuke Katayama, Kyoya Takano, Naoko Ono, Ryuichi Fujimoto:
98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits. IEEE J. Solid State Circuits 48(10): 2273-2284 (2013)
[c6]
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Kyoya Takano, Ryuichi Fujimoto, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima:
14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. RWS 2013: 235-237
2012
[j15]
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  - journals/ieicet/KatayamaMTFF12
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Kosuke Katayama, Mizuki Motoyoshi, Kyoya Takano, Ryuichi Fujimoto, Minoru Fujishima:
Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit. IEICE Trans. Electron. 95-C(6): 1077-1085 (2012)
[j14]
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Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Uroschanit Yodprasit, Minoru Fujishima:
A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology. IEICE Trans. Electron. 95-C(7): 1154-1162 (2012)
[c5]
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Naoko Ono, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima:
135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS. VLSIC 2012: 50-51
2011
[j13]
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  - journals/ieiceee/MotoyoshiFTF11
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Mizuki Motoyoshi, Ryuichi Fujimoto, Kyoya Takano, Minoru Fujishima:
140GHz CMOS amplifier with group delay variation of 10.2ps and 0.1dB bandwidth of 12GHz. IEICE Electron. Express 8(14): 1192-1197 (2011)
[j11]
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Ryuichi Fujimoto, Kyoya Takano, Mizuki Motoyoshi, Uroschanit Yodprasit, Minoru Fujishima:
Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz. IEICE Trans. Electron. 94-C(4): 589-597 (2011)
[j10]
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Kyoya Takano, Ryuichi Fujimoto, Kosuke Katayama, Mizuki Motoyoshi, Minoru Fujishima:
Analysis of De-Embedding Error Cancellation in Cascade Circuit Design. IEICE Trans. Electron. 94-C(10): 1641-1649 (2011)

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